Reverse Current Sensing Regulator System and Method

ABSTRACT

A reverse current sensing (RCS) regulator system and method is provided. One embodiment of the invention includes a RCS regulator system. The system comprises a RCS comparator that monitors a drain voltage of a LS FET and is configured to switch states at a zero crossing point to provide an indication of the start of a reverse current condition. The system further comprises a RCS evaluator that measures a drain voltage of the LS FET upon receiving an indication that the LS FET has been turned off by the driver logic circuit and adjusts an offset to the RCS comparator to adjust the trip point of the RCS comparator relative to the drain voltage if the measured drain voltage falls outside a predetermined threshold.

TECHNICAL FIELD

This invention relates to electronic circuits, and more specifically toreverse current sensing regulator system and method.

BACKGROUND

A switching regulator typically employs a high side metal-oxidesemiconductor field effect transistor (MOSFET) (HS FET) and a low sideMOSFET (LS FET) to switch power and to provide current to an outputinductor that is normally providing current in the direction of anoutput load. If the current goes backward from load, through LS FET, toground, it is termed as a reverse current, which dissipates electricalenergy stored in an output capacitor coupled to the output inductor. Toimprove power efficiency, this typical regulator can have a reversecurrent sensing (RCS) circuit to reduce or eliminate the reversecurrent. RCS offers a secondary benefit to the regulator's faultprotection. If there is a short between battery VCC and the output,there would be large or even damaging reverse current going through LSFET. The RCS function can detect this short condition and turn off LSFET.

Ideally an RCS function should shut off LS FET at the onset of currentreversal. However, in applications where the output inductor is small,the load voltage is high and the switching frequency is fast, an RCScircuit can have large errors associated with its limited response timeand propagation delay of the LS FET driver. At the time LS FET is shutoff by RCS function, reverse current may already overshoot to anunacceptable degree. This delay-caused error can significantlycompromise the efficiency of the regulator. A straight forward solutionto the issue seems to be introducing a certain amount of offset to theRCS function, such that it would react to reverse current somewhatearlier to compensate for the propagation delay. However, thisdesign-in-offset approach is often not practical as it is limited toknown application voltages and components. In reality the applicationcondition may be unknown during the product design phase.

SUMMARY

In one aspect of the invention, a reverse current sensing (RCS)regulator system is provided. The system comprises a driver logiccircuit that switches between alternately turning on and off a high sidefield effect transistor (HS FET) and a low side field effect transistor(LS FET) to provide an inductor current through an inductor and tocharge a capacitor and provide a regulator output voltage to a load. Thesystem further comprises a RCS comparator that monitors a drain voltageof the LS FET and is configured to switch states at a zero crossingpoint to provide an indication of the start of a reverse currentcondition, and a RCS evaluator that measures a drain voltage of the LSFET upon receiving an indication that the LS FET has been turned off bythe driver logic circuit and adjusts an offset to the RCS comparator toadjust the trip point of the RCS comparator relative to the drainvoltage if the measured drain voltage falls outside a predeterminedthreshold.

In another aspect of the invention, a RCS regulator system is providedthat comprises means for alternately turning on and off a HS FET and aLS FET to provide an inductor current through an inductor and to chargea capacitor and provide a regulator output voltage to a load. The systemfurther comprises means for monitoring a drain voltage of the LS FET andproviding an indication of a start of a reverse current condition, meansfor measuring a drain voltage of the LS FET upon receiving an indicationthat the LS FET has been turned off in response to the indication of thestart of a reverse current condition and means for determining if themeasured drain voltage falls outside a predetermined threshold. Thesystem also comprises means for providing a trim control signal if themeans for determining determines that the measured drain voltage fallsoutside the predetermined threshold and means for providing an offsetbased on the trim control signal to the means for monitoring to adjustthe trip point of the means for monitoring relative to the drainvoltage.

In yet a further aspect of the invention, a method of calibrating areverse current sensing regulator system is provided that alternatelyturns on and off a HS FET and a LS FET to provide an inductor currentthrough an inductor and to charge a capacitor and provide a regulatoroutput voltage to a load. The method comprises monitoring a drainvoltage of the LS FET to determine if the drain voltage has crossed azero crossing point, providing an indication of the start of a reversecurrent condition if the drain voltage has crossed the zero crossingpoint and measuring a drain voltage of the LS FET upon receiving anindication that the LS FET has been turned off in response to theindication of the start of a reverse current condition. The methodfurther comprises determining if the measured drain voltage fallsoutside a predetermined threshold and providing an offset relative tothe drain voltage to adjust the trip point determination of the zerocrossing point if the measured drain voltage falls outside apredetermined threshold.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an automatic self calibrating RCS regulator system inaccordance with an aspect of the present invention.

FIG. 2 illustrates an exemplary RCS evaluator in accordance with anaspect of the present invention.

FIG. 3 illustrates an automatic self calibrating RCS regulator systememploying one particular offset generator implementation in accordancewith an aspect of the present invention.

FIG. 4 illustrates a set of waveforms generated by SPICE simulationsemploying the system and illustrated in FIGS. 1-3.

FIG. 5 illustrates an example of a method of calibrating a RCS regulatorsystem in accordance with an aspect of the invention.

DETAILED DESCRIPTION

The present invention relates to electronics, and more specifically to alow-cost, high-accuracy automatic self calibrating reverse currentsensing (RCS) regulator system and method that operates over a widerange of regulator applications.

FIG. 1 illustrates an automatic self calibrating RCS regulator system 10in accordance with an aspect of the present invention. The system 10comprises a driver logic circuit 12 that switches between alternatelyturning on and off a high side metal-oxide semiconductor field effecttransistor (MOSFET) (HS FET) (N0) and a low side MOSFET (LS FET) (N1) toprovide an inductor current I_(L) through an inductor L0 and to charge acapacitor C0 and provide a regulator output voltage V_(OUT) to a load(not shown). A RCS comparator 18 monitors a drain voltage LS_FET_VD ofthe LS FET N1. In a light load condition, when HS FET N0 turns off andLS FET N1 turns on, inductor L0 current I_(L) first flows forward (fromground to output load) and gradually decays to zero and starts toreverse its direction (from output load back to ground). Thiscorresponds to the process that LS_FET_VD is first negative andapproaches zero and finally becomes positive causing a reverse currentthrough the inductor L0 and LS FET N1. The RCS comparator 18 isconfigured to switch states (low to high) at the zero crossing point toprovide an indication of the start of a reverse current, which is termedas an RCS event. Whenever an RCS event is detected, the driver logiccircuit 12 turns off the LS FET N1 until the next switching cycle. AnRCS function of monitoring for a RCS event and turning off the LS FET N1until the next switching cycle can be performed employing a variety ofdifferent circuit function techniques.

The system 10 includes an RCS evaluator 14 and an offset generator 16.At power up, the RCS evaluator 14 resets its logic states, letting theRCS comparator 18 operate at an design default offset (e.g., zerovolts). A first RCS event activates the automatic calibration process ofthe system 10. At this point, the RCS evaluator 14 measures LS_FET_VDupon receiving an indication that the LS FET has been turned off by theRCS function in the drive logic circuit 12. If the measured LS_FET_VD isreasonably close to zero, the RCS error is negligible, and the RCSevaluator 14 and the offset generator 16 take no action except formaintaining the existing calibration trim setting of the offsetgenerator 16 and monitoring for the next RCS event.

In normal cases, if the measured LS_FET VD is not zero but higher thanan accurate voltage reference Vth, a reverse current overshoot (RCSerror) has been detected. The RCS evaluator 14 then upgrades thecalibration trim setting, through the offset generator 16, to set theRCS comparator 18 to operate with more offset, so the RCS comparator 18will trip earlier in the following RCS events to correct for overshoot.This causes the voltage on the input terminal of the RCS comparator 18to increase relative to the LS_FET_VD, such that the comparator willtrip at a trip point where LS_FET_VD is below ground. After eachLS_FET_VD measurement followed by immediate trip point adjustment (ifneeded), the RCS evaluator checks the effect of trimming by repeatingthe evaluate-trim cycle until an extreme trim setting is reached, suchthat the measured LS_FET_VD is not higher than the accurate voltagereference Vth or a timer (one-shot) indicates a time out has occurred.Then the RCS evaluator 14 latches the final trim setting and becomesinactive. This trim-at-power up procedure not only saves power but alsotake advantage of the initial quieter time for calibration.

In a rare and opposite case, if the measured LS_FET_VD is not zero butlower than a reference voltage, a reverse current undershoot (also RCSerror) is detected (this could happen through over-trim for comparatoroffset in design). The RCS evaluator 14 immediately downgrades the trimsetting, so that the RCS comparator 18 will operate with less offset.The RCS comparator 18 thus will trip later to correct the undershooterror.

FIG. 2 illustrates an exemplary RCS evaluator 30 in accordance with anaspect of the present invention. Reverse current overshoot is the mostcommon error in an RCS function. Although, LS_FET_VD zero-crossing canbe easily and accurately detected with a voltage comparator, it is thepropagation delay for turning off the LS FET that causes the overshoot.The RCS evaluator 30 implemented in FIG. 2 handles this overshoot case.Shortly after power up of a system regulator, the system regulatornormally experiences a brief light load period and RCS events willtherefore be encountered. The first RCS event activates a timer 42 andtriggers RCS automatic calibration, indicated by signal ENA_CAL=high andsetting one input of sample control logic gate (AN210) to high. Asample/hold unit 32 comprising a sample switch S0, hold capacitor C2 andreset switch MN11 is coupled to a positive input terminal of acomparator 34. Applying a sample/hold stage into the RCS evaluatorprovides measurement immunity to interference from noise and circuitpropagation delay. The switch S0 can be designed to block high voltageand cancel charge injection during switching. When LS FET is on(LSD_ON), the sample switch S0 is open. When the LS FET turns off thesample switch S0 closes and stores LS_FET_VD into hold capacitor C2.Thus C2 contains information of the accuracy of the RCS function and iscompared to a reference voltage Vth (e.g., 20 mv) that is coupled to anegative input terminal of the comparator 34. If the reverse current hasa detectable overshoot, i.e., LS_FET_VD>Vth, an output (CMP_OUT) of thecomparator 34 goes high.

The output of the comparator 34 is coupled to an input of a rising edgedetector 36. The rising edge detector 36 includes a resistor R1, acapacitor C1 and a three input logic gate (AN311). Through the risingedge detector, the CMP_OUT transition produces a pulse called CLK_TRIMto advance a counter 38 by one count and resets the sample and holdcircuit 32 via a logic gate (NA211) and the reset switch MN11. Thecounter 38 provides a counter count trim value (COUNT_TRIM) to a decoder40, which provide a TRIM control signal to an offset generator forsetting an offset value. The RCS evaluator 30 checks the effect oftrimming by repeating the evaluate-trim cycle until an extreme trimsetting is reached turning off the timer 42 through logic gate (AN211)or a time out of the timer 42. Then the RCS evaluator 30 latches thefinal trim setting and becomes inactive. Without overshoot, i.e.,Vd<Vth, the count remains unchanged.

As pointed out earlier, there maybe a rare case where we need to detectundershoot and to adjust the RCS comparator to trip later. To make theautomatic calibration circuit handle this case, the counter 38 can be anup/down counter and a window comparator can be employed with or withoutthe comparator 34. If an overshoot condition is detected, the up/downcounter counts up and in the case that there is an undershoot condition,the up/down counter counts down. The functionality of the circuitry ofthe RCS evaluator 30 remains the same.

FIG. 3 illustrates an automatic self calibrating RCS regulator system 50employing one particular offset generator implementation in accordancewith an aspect of the present invention. The system 50 comprises adriver logic circuit 52 that switches between alternately turning on andoff a high side MOSFET (HS FET) M1 and a low side MOSFET (LS FET) M2 toprovide an inductor current through an inductor L1 and to charge acapacitor C3 and provide a regulator output voltage to a load (notshown). A RCS comparator 56 monitors the drain voltage LS_FET_Vd of theLS FET M2 and is configured to switch states (low to high) at the zerocrossing point to provide an indication of the start of an RCS event.Whenever an RCS event is detected, the driver logic circuit 52 turns offthe LS FET M2 until the next switching cycle. The system 50 includes aRCS evaluator 54 similar to the RCS evaluator of FIG. 1 and an offsetgenerator 58. The offset generator 58 is configured to provideappropriate offset to the RCS comparator 56 and provides the referencevoltage Vth. The reference voltage Vth is provided by a current sourceI_Vth and a matching transistor M_Vth. The matching transistor M_Vth ismatched to the LS FET M2. Vth is generated by forcing an accuratecurrent, I_Vth, into transistor M_Vth. Vth should be accurate andinsensitive to PVT variations. To this end, I_Vth can be trimmed to adesign spec and zero TC during IC production test and transistor M_Vthis designed to match LS FET. If the LS FET Rds(on) is 0.2 ohm nominal,the maximum allowed RCS overshoot current is 100 mA, then RCS comparatortrip point is determined by Vth=0.2 ohm*100 mA=20 mV. In the FIG. 3example, I_Vth=10 uA, so Rds(on) of M_Vth should be 2 k ohm.

The offset generator 58 includes current sources IS1, IS2 and IS3 thatprovide offset currents with increasing values. The current sources IS1,IS2, IS3 are coupled at one end to a supply voltage VCC and at the otherend to a common node (CN) through respective trim control transistorsM0, M3 and M4. The common node CN is coupled to LS_FET_VD of the LS FETthrough a resistor R2. An anode of a diode D1 is coupled to a positiveinput terminal of the RCS comparator 56 and the cathode is coupled tothe common node CN. An anode of a diode D2 is coupled to a negativeinput terminal of the RCS comparator 56 and the anode of the diode D2 iscoupled to ground through a resistor R3. A current source IB1 is coupledbetween the supply voltage VCC and the negative input terminal of theRCS comparator 56 and a current source IB2 is coupled to a positiveinput terminal of the RCS comparator 56. The current sources IB1, IB2,diodes D0, D1 and resistors R2 and R3 are matched such to provide equaloffsets to the positive and negative input terminals of the RCScomparator 56 as the design default offset at initialization of thesystem 50. IB1 and IB2 provide necessary DC bias to level-shiftingdiodes D0 and D1, without which it is difficult for the comparator 56 tosense a high speed negative voltage of LS_FET_VD. D0 can also aid inhigh voltage protection and clamping. R2 and R3 can also be employed inESD and latch up protection.

In the present example, IB1=IB2=3 μamps and R2=R3=2 Kohms, such that anoffset of 0.706 Volts (diode drop (0.7)+Resistor drop (3 μamps*2 Kohms))is added to ground at the negative input terminal of the RCS comparator56 and to the LS_FET_VD at the positive input terminal of the RCScomparator 56. In this manner, the RCS event should occur at 0 volts atthe initialization setting since the same offset has been added to bothinput terminals of the RCS comparator 56.

At power up, the RCS evaluator 54 resets its logic states, letting theRCS comparator 56 operate at an design default offset (e.g., zerovolts). That is each of the trim control transistors M0, M3 and M4 areoff and the same offset voltage is provided at both input terminals ofthe RCS comparator by the current sources IB1 and IB2. A first RCS eventactivates the automatic calibration process of the system 50. At thispoint, the RCS evaluator 54 measures LS_FET_VD upon receiving anindication that the LS FET has been turned off by the RCS function inthe drive logic circuit 52. If the measured LS_FET_VD is reasonablyclose to zero, the RCS error is negligible, and the RCS evaluator 54 andthe offset generator 58 take no action except for maintaining theexisting calibration trim setting of the offset generator 58 andmonitoring for the next RCS event. If the measured LS_FET_VD is not zerobut higher than the accurate voltage reference Vth, a reverse currentovershoot (RCS error) has been detected. The RCS evaluator 54 thenupgrades the calibration trim setting, through the offset generator 58turning on M0 and providing an adding 2 μA to IB2 through R2 causing theLS_FET_VD trip point to be 4 mV below ground and the voltage on theinput terminal of the RCS comparator 56 to increase relative to theLS_FET VD by 0.710 volts.

The RCS evaluator 54 checks the effect of trimming by repeating theevaluate-trim cycle. If the measured LS_FET_VD is not zero but higherthan the accurate voltage reference Vth, the RCS evaluator 54 thenupgrades the calibration trim setting, through the offset generator 58turning off M0 and turning on M3 and adding 4 μA to IB1 through R2causing the LS_FET_VD trip point to be 8 mV below ground and the voltageon the input terminal of the RCS comparator 56 to increase relative tothe LS_FET_VD by 0.712 volts. The RCS evaluator 54 can the checks theeffect of trimming by repeating the evaluate-trim cycle. If the measuredLS_FET_VD is not zero but higher than the accurate voltage referenceVth, the RCS evaluator 54 then upgrades the calibration trim setting,through the offset generator 58 turning off M3 and turning on M4 andproviding an adding 6 μA to IB2 through R2 causing the LS_FET_VD trippoint to be 12 mV below ground and the voltage on the input terminal ofthe RCS comparator 56 to increase relative to the LS_FET_VD by 0.716volts. Then the RCS evaluator 54 latches the final trim setting andbecomes inactive.

The current sources IS1, IS2 and IS3 can be accurately trimmed duringproduction testing to cancel out manufacturing variations of R2 and havevirtually zero temperature coefficients (TC). Therefore, the IR drop byoffset currents on R2 is not sensitive to variations of process, voltageand temperatures (PVT). This means the offset created by R2 (not by D0)will not change due to PVT variations. In the present example, only oneof the offset currents can be turned on by switches M0, M3, M4 each timefor comparator's trip point adjustment. It is to be appreciated that theswitches can be turned on by a binary coded signal such that the offsetcurrents can be additive from 000 (all currents sources off) to 111 (allcurrent sources on). Although a set of 3 switches and 3 offset trimcurrents is illustrated, for higher precision trimming, more offset trimbits can be employed for more current switches which can be added inparallel with M0, M3 and M4. Another way of implementing offsets to thecomparator 56 is to adjust bias currents inside the RCS comparator 56.

FIG. 4 illustrates a set of waveforms 70 generated by SPICE simulationsemploying the system and illustrated in FIGS. 1-3. As illustrated inFIG. 4, a first RCS event (waveform 72) triggers the one-shot timer 42so signal ENA_CAL goes high (waveform 74). At a second RCS event(waveform 72), the RCS evaluator decides there is reverse currentovershoot (see initial large negative spikes in the Inductor current inwaveform 84) so the counter 38 advances by 1 count at the CLK TRIM pulse(waveform 76). The decoder 40 thus sets TRIM<1> high (waveform 78). Atthe third RCS event (waveform 72), the RCS evaluator again detects anovershoot, which is of smaller amplitude (waveform 84) due to thetrimming just applied. The RCS evaluator therefore determines that thepreviously selected TRIM<1> is not sufficient so the counter 38 advancesby another count at the second CLK_TRIM pulse (waveform 76). The decoder40 changes trimming by selecting TRIM<2> (waveform 80). At later 4-7 RCSevents (waveform 72), the evaluator decides TRIM<2> setting is adequatebecause there is no longer large overshoot (waveform 82) (see finalsmall negative spikes in the Inductor current in waveform 84). Automaticcalibration is finished at a 7th RCS events indicated by ENA_CAL goinglow (waveform 74). The counter and trim selection remain unchanged untilthe regulator powers down.

In view of the foregoing structural and functional features describedabove, certain methods will be better appreciated with reference to FIG.5. It is to be understood and appreciated that the illustrated actions,in other embodiments, may occur in different orders and/or concurrentlywith other actions. Moreover, not all illustrated features may berequired to implement a method. It is to be further understood that thefollowing methodologies can be implemented in hardware (e.g., analog ordigital circuitry, such as may be embodied in an application specificintegrated circuit), software (e.g., as executable instructions storedin memory or running on a processor implemented in an ASIC), or anycombination of hardware and software.

FIG. 5 illustrates an example of a method 100 of calibrating a RCSregulator system in accordance with an aspect of the invention. The RCSregulator system alternately turns on and off a HS FET and a LS FET toprovide an inductor current through an inductor and to charge acapacitor and provide a regulator output voltage to a load. The method100 begins at 102 where the system is powered up and an offset designdefault is set to a RCS comparator. At 104, a drain voltage of the LSFET is monitored by the RCS comparator to determine if the drain voltagehas crossed a zero crossing point. At 106, an indication is provided atthe start of a reverse current condition if the drain voltage hascrossed the zero crossing point. At 108, a drain voltage of the LS FETis measured upon receiving an indication that the LS FET has been turnedoff in response to the indication of the start of a reverse currentcondition. At 110, a determination of if the measured drain voltagefalls outside a predetermined threshold is made and an offset relativeto the drain voltage to adjust the trip point determination of the zerocrossing point is provided if the measured drain voltage falls outside apredetermined threshold. The methodology 100 can be repeated for aplurality of switching cycles until the measured drain voltage fallswithin the predetermined threshold or a time out has occurred.

What have been described above are examples of the invention. It is, ofcourse, not possible to describe every conceivable combination ofcomponents or methodologies for purposes of describing the invention,but one of ordinary skill in the art will recognize that many furthercombinations and permutations of the invention are possible.Accordingly, the invention is intended to embrace all such alterations,modifications, and variations that fall within the scope of thisapplication, including the appended claims.

1. A reverse current sensing (RCS) regulator system comprising: a driverlogic circuit that switches between alternately turning on and off ahigh side field effect transistor (HS FET) and a low side field effecttransistor (LS FET) to provide an inductor current through an inductorand to charge a capacitor and provide a regulator output voltage to aload; a RCS comparator that monitors a drain voltage of the LS FET andis configured to switch states at a zero crossing point to provide anindication of the start of a reverse current condition; and a RCSevaluator that measures a drain voltage of the LS FET upon receiving anindication that the LS FET has been turned off by the driver logiccircuit and adjusts an offset to the RCS comparator to adjust the trippoint of the RCS comparator relative to the drain voltage if themeasured drain voltage falls outside a predetermined threshold.
 2. Thesystem of claim 1, further comprising an offset generator that providesan offset voltage to the RCS comparator in response to a trim controlsignal from the RCS evaluator.
 3. The system of claim 1, wherein the RCSevaluator repeats the measuring of the drain voltage and adjusting theoffset to the RCS comparator for each switching cycle until the measureddrain voltage falls within the predetermined threshold or a time out hasoccurred.
 4. The system of claim 2, wherein the offset generatorcomprises: a plurality of current sources and respective series coupledtrim control transistors being coupled in parallel and connected to oneanother at a common node; a first resistor coupled between the commonnode and the drain voltage; and a first diode having an anode coupled toa first input terminal of the RCS comparator and a cathode coupled tothe common node wherein the RCS evaluator can vary the offset to the RCScomparator relative to the drain voltage by varying the selection of theplurality of current sources employing the respective series coupledtrim control transistors.
 5. The system of claim 4, wherein the offsetgenerator further comprises: a second diode having an anode coupled to asecond input terminal of the RCS comparator and a cathode coupled toground through a second resistor; a first design default offset currentsource coupled to the first input terminal of the RCS comparator toprovide a first design default offset to the first input terminal; asecond design default offset current source coupled to the second inputterminal of the RCS comparator to provide a second design default offsetto the second input terminal wherein the first and second design defaultoffset current sources, the first and second diodes, and the first andsecond resistors are matched to provide equal offsets to the first andsecond input terminals of the RCS comparator as the design defaultoffset at initialization of the system.
 6. The system of claim 1,wherein the RCS evaluator comprises: a sample and hold circuit thatsamples the drain voltage of the LS FET upon receiving an indicationthat the LS FET has been turned off; a threshold comparator thatcompares the measured voltage to a predetermined voltage and provides alogic transition in response to the measured drain voltage fallingoutside a predetermined threshold, wherein the RCS evaluator adjusts atrip point of the RCS comparator relative to the drain voltage inresponse to the logic transition.
 7. The system of claim 6, wherein theRCS evaluator further comprises: an edge detector that generates a clocktrim signal that indicates that a logic transition has occurred at thethreshold comparator; a counter that increments and/or decrements inresponse to the clock trim signal; and a decoder that changes a state ofa trim control signal to adjust an offset to the RCS comparator based onan output value of the counter.
 8. The system of claim 7, wherein theRCS evaluator repeats the sampling by the sample and hold detector,comparing by the threshold detector, logic transition detecting by theedge detector, counting by the counter and state changing by the decoderto adjust an offset to the RCS comparator for each switching cycle untilthe measured drain voltage falls within the predetermined threshold or atimer provides an indication that a time out has occurred.
 9. The systemof claim 1, wherein the RCS evaluator increases the offset to the RCScomparator to adjust the trip point of the RCS comparator relative tothe drain voltage if the measured drain voltage falls below apredetermined threshold and the RCS evaluator decreases an offset to theRCS comparator to adjust the trip point of the RCS comparator relativeto the drain voltage if the measured drain voltage is above apredetermined threshold.
 10. The system of claim 1, wherein thepredetermined threshold is set by a current source and a FET that ismatched to the LS FET.
 11. A reverse current sensing (RCS) regulatorsystem comprising: means for alternately turning on and off a high sidefield effect transistor (HS FET) and a low side field effect transistor(LS FET) to provide an inductor current through an inductor and tocharge a capacitor and provide a regulator output voltage to a load;means for monitoring a drain voltage of the LS FET and providing anindication of a start of a reverse current condition; means formeasuring a drain voltage of the LS FET upon receiving an indicationthat the LS FET has been turned off in response to the indication of thestart of a reverse current condition; means for determining if themeasured drain voltage falls outside a predetermined threshold; meansfor providing a trim control signal if the means for determiningdetermines that the measured drain voltage falls outside thepredetermined threshold; and means for providing an offset based on thetrim control signal to the means for monitoring to adjust the trip pointof the means for monitoring relative to the drain voltage.
 12. Thesystem of claim 11, wherein the means for monitoring, the means formeasuring, the means for determining and the means for providing a trimcontrol signal repeats for each switching cycle until the measured drainvoltage falls within the predetermined threshold or a time out hasoccurred.
 13. The system of claim 12, wherein the means for providing atrim control signal comprises means for counting a number of times themeasured drain voltage falls outside of the predetermined threshold fora plurality of switching cycles and means for providing the trim controlsignal based on the count of the means for counting.
 14. The system ofclaim 13, further comprising means for providing a design default offsetat initialization of the system.
 15. The system of claim 11, wherein theoffset relative to the drain voltage is increased if the measured drainvoltage falls below a predetermined threshold and/or decreased if themeasured drain voltage falls above a predetermined threshold.
 16. Amethod of calibrating a reverse current sensing (RCS) regulator systemthat alternately turns on and off a high side field effect transistor(HS FET) and a low side field effect transistor (LS FET) to provide aninductor current through an inductor and to charge a capacitor andprovide a regulator output voltage to a load, the method comprising:monitoring a drain voltage of the LS FET to determine if the drainvoltage has crossed a zero crossing point; providing an indication ofthe start of a reverse current condition if the drain voltage hascrossed the zero crossing point; measuring a drain voltage of the LS FETupon receiving an indication that the LS FET has been turned off inresponse to the indication of the start of a reverse current condition;determining if the measured drain voltage falls outside a predeterminedthreshold; and providing an offset relative to the drain voltage toadjust the trip point determination of the zero crossing point if themeasured drain voltage falls outside a predetermined threshold.
 17. Thesystem of claim 16, wherein the monitoring, providing, measuring,determining and providing is repeated for each switching cycle until themeasured drain voltage falls within the predetermined threshold or atime out has occurred.
 18. The system of claim 17, further comprisingcounting a number of times the measured drain voltage falls outside ofthe predetermined threshold for a plurality of switching cycles andproviding the offset based the count.
 19. The system of claim 16,further comprising providing a design default offset at initializationof the method.
 20. The system of claim 11, wherein the offset relativeto the drain voltage is increased if the measured drain voltage fallsbelow a predetermined threshold and/or decreased if the measured drainvoltage falls above a predetermined threshold.